A version of the PCI computer bus that uses existing PCI programming concepts, but bases it on a completely different and much faster serial physical-layer communications protocol.
PCI Express was developed to overcome the limitations of the original PCI bus. As developed over a decade ago, the original PCI bus operated at 33MHz and 32 bits with a peak theoretical bandwidth of 132MB per second. It used a shared bus topology, with bus bandwidth shared among multiple devices, to enable communication among the different devices on the bus. As devices evolved, new bandwidth-hungry devices began starving other devices on the same shared bus. Gigabit Ethernet cards, for example, can monopolize up to 95% of available PCI bus bandwidth.
The PCI Express bus is no longer a single parallel data bus through which all data is routed at a set rate. Rather, an assembly of serial, point-to-point wired, individually clocked “lanes, each consisting of two pairs of data lines, carry data upstream and downstream. Since it’s based on the existing PCI system, cards and systems can be converted to PCI Express by changing the physical layer only – existing systems could be adapted to PCI Express without any change in software. The higher speeds on PCI Express (ranging from 250Mbps to 4,000Mbps) allow it to replace almost all existing internal buses, including AGP and PCI.
The biggest impact that PCI Express has made to date is with the PCIe x16 graphics slot. Found in the latest Intel and AMD-based chipsets, this implementation of PCI Express is now preferred over AGP 8x as a platform for graphics card manufacturers