Acronym for Complex Instruction Set Computer. This is an instruction set architecture (ISA) in which each instruction to a CPU can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. The original theory was to have the processor receive fewer instructions, which would allow it to handle “high-level” programming languages more easily. This is in contrast to Reduced Instruction Set Computer (RISC) design, which executes a rapid sequence of simple instructions.
Before the first RISC processors were designed, many computer architects were trying to design instruction sets to support high-level languages by providing “high-level” instructions such as procedure call and return, loop instructions such as “decrement and branch if non-zero” and complex addressing modes to allow data structure and array accesses to be compiled into single instructions.
While these designs achieved their aim of allowing high-level language constructs to be expressed in fewer instructions, they did not always result in improved performance. For example, on one processor it was discovered that it was possible to improve the performance by NOT using the procedure call instruction but using a sequence of simpler instructions instead. Furthermore, the more complex the instruction set, the greater the overhead needed to decode an instruction, both in execution time and silicon area.
The term, like its antonym RISC, has become less meaningful with the continued evolution of both CISC and RISC designs and implementations. Modern “CISC” CPUs, such as the Pentium 4, while they usually support every instruction that their predecessors did, are designed to work most efficiently with a subset of instructions more resembling a typical “RISC” instruction set. Indeed, many CISC CPUs (such as modern x86 processors from both Intel and AMD) “break” many x86 instructions into a series of smaller internal “micro-operations” that are then executed internally by the processor.